1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a trench isolation structure and a method of forming the trench isolation structure.
2. Description of the Related Art
As the integration of semiconductor devices has increased and feature size has decreased, trench isolation regions have been reduced accordingly. Also, the portable devices that are in widespread use today generally require a low voltage power supply for operation. Therefore, this trend toward high density and low consumptive power characteristics requires continued improvement in semiconductor device fabrication methods.
Trench isolation, which is one of the initial steps in a semiconductor device manufacturing process, affects the size of active areas and process margins in subsequent processes. Trench isolation methods are the most common isolation method for highly integrated semiconductor devices.
In one conventional trench isolation method, a trench is formed by etching a silicon substrate and then filling it with a dielectric material using a chemical vapor deposition (CVD) method. Next, an isolating layer is formed in the trench by planarizing the filled structure using a chemical mechanical polishing (CMP) method.
However, when the density of an isolation area increases, the aspect ratio of the trench increases and it becomes more difficult to fill the trench with the dielectric material using the CVD method without the occurrence of voids.
Moreover, in this conventional method, after the isolation area is formed, the silicon substrate is excessively stressed by subsequent high temperature thermal treatment and oxidation processes. As a result, silicon lattice defects such as dislocation occur, and an active area near the corner of the trench which defines the isolation area is oxidized.
Accordingly, to prevent the above problems, another technique has been utilized. According to this technique, before a dielectric material is filled in a trench, a thin oxide layer is formed on the inner wall of the trench. Next, a silicon nitride liner is formed on the oxide layer to a thickness of about 100xcx9c700 xc3x85 (angstroms). This prevents the silicon substrate from being excessively stressed by subsequent high thermal treatment and oxidation processes. In this case, the stress to a silicon substrate is relieved by forming a silicon nitride liner in a trench, and an active area in the silicon substrate is prevented from being oxidized near the corner of the trench.
The remaining space in the trench, which is lined with the silicon nitride liner, is fully filled with a dielectric material. Then a general wet etching process is performed using phosphoric acid to remove a silicon nitride layer which was used as an etching mask when the trench was formed. However, if the silicon nitride liner has a thickness of 100 xc3x85, it is etched along with the silicon nitride layer during the wet etching process. As a result, dents form between the isolation area and the active area. The dents in the substrate can cause certain problems, such as a double turn-on phenomenon in a transistor, i.e., a hump phenomenon. In addition, there may be a decrease in the threshold voltage in those semiconductor devices manufactured using a substrate having dents. Also, a polysilicon residue used as a gate electrode material may create a bridge between adjacent gate electrodes, thereby deteriorating the electrical properties of a semiconductor device.
To solve the above problems, it is an object of the present invention to provide a semiconductor device with a trench isolation region having a large aspect ratio without voids, and a substrate that is dent-free between an isolation area and an active area.
It is another object of the present invention to provide a trench isolation method capable of filling a trench having a large aspect ratio with a dielectric material, by which method voids are not formed inside a trench isolation region, dents are not formed between an isolation area and an active area, a silicon substrate is effectively prevented from being excessively stressed, and the active area is effectively prevented from being oxidized near the corner of the trench.
Accordingly, to achieve the above first object, there is provided a semiconductor device including a silicon substrate and a trench isolation region having a bottom surface and sidewalls, and being formed in the silicon substrate to isolate adjacent two active areas. A silicon epitaxial growth layer contacts the silicon substrate at the bottom surface of the trench isolation region and fills the lower half of the trench isolation region. A first oxide layer has an L-shaped cross-section. and extends from the sidewall of the trench isolation region to a portion of the bottom surface of the trench isolation region. An anti-oxidative liner has an L-shaped cross-section and extends between the first oxide layer and the silicon epitaxial growth layer. The surface of the anti-oxidative line contacts the silicon epitaxial growth layer. A second oxide layer fills the upper half of the trench isolation region on the silicon epitaxial growth layer. The silicon substrate has a crystal orientation of [100]. The first oxide layer is formed of thermal oxide and the anti-oxidative liner has a thickness of 50xcx9c70 xc3x85. The anti-oxidative liner is formed of silicon nitride (Si3N4), boron nitride (BN), or alumina (Al2O3). The semiconductor device may further include an oxide liner interposed between the anti-oxidative liner and the second oxide layer.
To achieve the second object, there is provided a trench isolation method. In the trench isolation method, a trench is formed to a predetermined depth in a silicon substrate. A first oxide layer is formed on a bottom surface and sidewalls of the trench. An anti-oxidative liner is formed on the first oxide layer. The semiconductor substrate is exposed at the bottom surface of the trench by partially removing the anti-oxidative liner and the first oxide layer. A silicon epitaxial growth layer, partially filling the inside of the trench defined by the antioxidative liner, is formed by selectively epitaxially growing silicon from the exposed silicon substrate. A second oxide layer is formed on the silicon epitaxial growth layer to fully fill the trench.
Exposing the semiconductor substrate at the bottom surface of the trench includes: forming a protective oxide layer on the entire surface of the resultant structure having the anti-oxidative liner; etching back the protective oxide layer to form a protective spacer covering the anti-oxidative liner extended along the sidewalls of the trench and to expose the silicon substrate at the bottom surface of the trench; and removing the protective spacer. The protective spacer is removed by a wet etching method or a dry etching method. After exposing the semiconductor substrate at the bottom surface of the trench, a sacrificial oxide layer is formed on the exposed silicon substrate and the sacrificial oxide layer is removed. The silicon epitaxial growth layer is formed on the silicon substrate from which the sacrificial oxide layer is removed. After forming the silicon epitaxial growth layer, an oxide liner is formed on the exposed surface of the anti-oxidative liner, and the second oxide layer is formed on the oxide liner.
According to the present invention, the aspect ratio of the inside of the trench to be filled decreases in a deposition process for filling the trench and thus voids are not formed inside the trench. Also, an anti-oxidative liner is formed in the trench isolation region of the semiconductor device. The anti-oxidative liner is thin enough to minimize etch wastage caused by a subsequent wet etching solution, and thus it can efficiently prevent a silicon substrate from being excessively stressed and an active area from being oxidized near the corner of the trench. Further, no dents are formed between the isolation area and the active area, thereby improving the electrical properties of the semiconductor devices.